1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device with an isolation layer buried in a trench, an electronic device having the same, and a method for fabricating the same.
2. Description of the Related Art
A semiconductor device includes an isolation layer to isolate adjacent unit components from each other, and the isolation layer is formed through a shallow trench isolation (STI) process. The key steps of the STI process involve forming a trench in a substrate and burying a dielectric material in the trench to form an isolation layer. The STI process may be applied to a process for fabricating a very large scale integrated semiconductor device, for example, one or more gigabyte DRAM.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating an isolation layer of a semiconductor device.
Referring to FIG. 1A, a mask pattern (not illustrated) is formed over a substrate 11 having a first region and a second region, and trenches are formed by etching the substrate 11 using the mask pattern as an etch barrier. At this time, the trenches include a first trench 12A formed in the first region and a second trench 12B formed in the second area, and a first critical dimension CD1 of the first trench 12A is smaller than a second critical dimension CD2 of the second trench 12B due to a difference between the densities of unit components (for example, transistors) formed in the first and second regions.
Referring to FIG. 1B, an interface layer 13 and a liner layer 14 are sequentially formed on the surface of the first and second trenches 12A and 12B.
Referring to FIG. 1C, a gap-fill layer 15 is formed on the liner layer 14 so as to fill the first and second trenches 12A and 12B, and a planarization process is performed until the surface of the substrate 11 is exposed, thereby completing an isolation layer 100.
In the conventional method, the interface layer 13 is formed on the surface of the second trench 12B in the second region at the same time as the interface layer 13 is formed on the surface of the first trench 12A in the first region. Therefore, the thickness of the interface layer 13 in the first region is equal to that of the interface layer 13 in the second region.
Meanwhile, with the increase in integration degree of the semiconductor device, the first critical dimension CD1 of the first trench 12A is reduced to thereby decrease a process margin in forming the liner layer 14 and the gap-fill layer 15 in the first trench 12A.
In order to secure such a margin, a method of reducing the thickness of the interface layer 13 has been proposed in the first region. However, since the interface layer 13 is formed in the first and second regions at the same time, thickness of the interface layer 13 is reduced in the second region as well, thereby degrading hot electron induced punchthrough (HEIP) effect in the second region.